Tag Archives: Wafer Probe

Protecting Wafer Probe Total Cost of Ownership (TCO)

If you’re a probe customer, or thinking of becoming one, we want to make sure that you are not only completely satisfied with your on-wafer probe, but that you’re positioned to maximize yo… [View More]

Challenges with Wafer Probing on Fine-Pitch Micro-Bumps for 2.5D- and 3D-SICs

Recent advances in semiconductor processing technology enable the manufacturing of integrated circuits with Through-Silicon Vias (TSVs). TSV is a conducting “nail” that provides an electri… [View More]

Small Pad Probing to 40 Microns with InfinityQuad™ Technology

With using conventional, multi-contact mixed-signal wafer probes for contacting small pads, there are a number of issues we see with traditional wafer probe technologies. First, a lot of the probes ha… [View More]

Complexity Issues in 4-Port RF Design Architectures

Probe-based 4-port device measurements have some unique challenges. Variation in wafer probe location on a calibration standard may cause electrical behavior to vary from the defined standard paramete… [View More]

Addressing Challenges to 4-Port On-Wafer Probe Measurements

When moving from 2-port measurements to 4-port device measurements, the first thing you might ask is, “Can my 2-port methods be directly applied to 4-port?” The answer is clearly: NO. Seve… [View More]